: A unified verification automation solution that creates plug&play test benches for many complex ASICs spanning architecture, RTL, emulation, to silicon bring-up. The engine inside Draco VA not only generates exhaustive functional scenarios automatically and systematically but also provides assertion interface to automate debugging. As a result, the verification engineers' productivity is at least doubled. More...

PCIE-VR Lite is available for FPGA designers.

PCIE-VR supports the latest version of PCIE standard. It verifies all Gen1/Gen2/Gen3 PCIE ASIC and FPGA designs, such as root complex, switches, end points, and bridges at both Register-Transfer Level (RTL) and Electronic System Level (ESL). IO Virtualization is supported.

PCIE-VR can be integrated to an emulator via standard SCE-MI interface.

Read more about PCIE-VR in the product page.

The SATA-VR Verification IP is in full compliance with the latest Sata standard. Its automatic state machine exercisers enable the shortest possible verification time with the full coverage of state machines at the physical and data link layers. Moreover, its 1510D-compatible DMA engines and a de-facto standard ATA/ATAPI Linux driver running on top of the DUT not only ensures the backward compatibility but also enables the most efficient verification automation at the transport layer and layers above.

Read more about SATA -VR in the product page.



The SERDES-VR Verification IP is providing effective way to verify serdes module functionality. Serial, eight-bit, ten-bit encoded, sixteen-bit, and twenty-bit interfaces are provided to device under test. Various range of protocols are supported including PCI-Express, SATA, Ethernet XAUI/XGXS, 10/100/1000 SGMII, 1000BaseX, Fibre Channel, Sonet, Infiniband, and so on.

Read more about SERDES -VR in the product page.