Automatic Driver Generator (ADG)

Transform ASIC Internals into a Set of Properties in SDL

The SDL and RTL characterize the design and verification environment extensively in the form of object properties. Each property associated with an object augments the controllability of the system. The automatic driver generator (ADG) is the core engine to process the SDL representation such that target design and testbench are configured as intended.

ASIC Configuration without Programming

As driver bridges between software program and silicon implementation, ADG incorporates SDL contexts provided by test writer into any stage of design chain such as architecture model, register transfer level implementation, emulation, or hardware prototype. In that perspective, the ADG serves a role of virtual and universal driver that enables verification engineer to maneuver the system without programming and detailed implementation entanglement. Simply put, the SDL is abstract characteristics of the system, and the ADG is the SDL interpreter. Hence, the SDL associated with ADG isolates test case development from time-consuming programming work, which makes verification process simple, fast and effective.

Key Features

  • Universal driver applicable to any stage of design chain such as architectural model, register transfer level design, emulator, FPGA prototypes, and real silicon

  • Orchestration of concurrent simulation/emulation and verification tasks incorporated by multiple thread management.

  • Software-accessible register and memory control and monitoring through direct poking and bus-transaction

  • Ordered configuration of the SoC observing temporal regulations between configuration events.

  • Automatic and exhausted register and memory testing based on access property

  • Random access to configurable registers and memories to model arbitrary software access to hardware.

  • Post-simulation analysis and statistic checking.