Test Scenario Generation at the Electronic System Level

Test  scenario is a reference set of input and output transaction sequences and associated tables that describe the relationships among the transactions. The transactions becomes stimulus and expected output on major DUT internal and external interfaces. By generating transactions at the Electronic System Level (ESL), the simulation environment is simplified dramatically and more CPU power is allocated to DUT during simulation.

Moreover, the DUT is freed from its form with Draco. The DUT can be a C model, an RTL design, or downloaded to an emulator or FPGA prototype board. Regardless the location of the DUT, all of them run the same test scenarios. There is no need to have different, but duplicated, test cases for C model, RTL simulation, and FPGA emulation.

Networking Architecture Simulator (ASIM)

Networking Architecture Simulator (ASIM) is a program and a library that models a computer network topology, ISO network layers, network traffic, and standard network protocols at the ESL. The result of such modeling generates a set of flows and packets (transactions) that move across the modeling points. Information tables for port mapping, routing, and classification are also generated for the DUT configuration.

Supports Standards

When used with Draco’s Design Interface Modules, ASIM generates golden scenarios that are fully complied to the following standards:

  • Ethernet

    • Fast Ethernet (802.3u)

    • 1Gbps (802.3z, 802.3ab)

    • 10Gbps (802.3ae)

    • Flow control (802.3x)

    • Link Aggregation (802.3ad)

    • Logic Link Control (802.2, LLC/SNAP)

    • Jumbo packet

    • VLAN tagging (802.1q)

  • Internet Protocols

    • PPP

    • Cisco HDLC

    • MPLS

    • IP

    • TCP

    • UDP

  • Fibre Channel

    • F/N/L ports

    • iSCSI

  • MPEG

    • Transport Stream

  • USB

Draco Architecture
System Description Language
Test Scenario Generator
Predicate-based Random Test Generator
Automatic Driver Generator
Dynamic Simulation Control
Assertion Model Builder
Design Interface Module