Predicate Random Test Generator (PRTG)

PRTG implements a super-layer of randomization that delegates power to create random sets of test cases in SDL. Such a specification is effective on both internal signals and external verification knobs. Internal signals including register bits and memory contents are set to the special value in resulting SDL test suites chosen from realistic vector space with equal or weighted probability. The accuracy of the PRTG outcome is secured by well-defined constraints expressed in meta-SDL as an input to the PRTG. Constraints specified in meta-SDL refine the SDL in that the correlation between configurable variables in DUT is properly tuned up, thus yielding solid and meaningful test cases. The degree of randomness is controlled by constraints. In that context, test cases created by PRTG can be classified into targeted-random testing. In addition to internal signals, external environment variables are controlled by PRTG to produce meaningful test cases.

To see how PRTG works, please click the following example,

Key Features

  • Targeted random-test creation based on well-defined constraints described in straightforward meta-SDL description.

  • Constraints specification in meta-SDL that incorporates extensive expressive power and built-in utility procedures.

  • Random test case template in meta-SDL can be reused over the chip generation.

  • Debugging tool enabling test writers to generate meaningful random test suites.

  • Static random test generation leverages debugging in case of flaw detection.