A New Class of Transactors: Simulation Functionality and Emulation Performance
When ASIC verification is performed with a software simulator, behavioral models are used to provide stimuli and collect output. Some important test features, such as IPG control and error injection, are easy to implement. When an emulator is used for ASIC verification, slow-down bridges and protocol testers are used to interface designs. This configuration has limitations that certain tests can not be created, such as precise IPG control and error injection mentioned before. Moreover, the emulator has different ways of programming and maintained by a different team. As a result, test cases created with the behavioral models that run on the software simulator cannot be reused on the emulator that uses slow-down bridges and protocol testers. It is virtually impossible to share the hard work that engineers have done in one world to the other.
Replace Slow-Dow Bridge Used in ASIC Emulation
Tarek introduces a new class of transactors that unify both worlds. We call them Emulatable Design Interface Modules (EDIM). EDIM is a hybrid of the emulation Slow-down Bridge and simulation behavioral model. Although EDIM can run at more than 150 MHz on an FPGA board, it is designed to be functional equivalent to its corresponding behavioral model precisely down to the clock at the interface. This gives you the power of running the same simulation test cases, i.e., regression suites, on the FPGA board.
What Inside EDIM
EDIM has hardware and software parts. The hardware part is a PCI or PCIE core connected to the WISHBONE bus. Different DUT interfaces are connected to the WISHBONE bus via interface adaptors. Basically, interface adaptors are made of control circuit and FIFO with DMA capability. The PCI or PCIE core is capable of running from 0 to 33MHz (PCI) or 100MHz (PCIE), the WISHBONE bus is from 0 to 166MHz, and the interfaces are from 0 to whatever matching clock rate in DUT. For example, the Ethernet EDIM has 16 X/G/MII ports. All of them are full duplex and can run up to 2MHz per port simultaneously when the PCI core (32bitX33MHz) is used. EDIM hardware is scalable not only by the clocks but also by the number of interface adaptors. Due to the DMA feature, the bus is dynamically requested and allocated when hardware has a need. There is no software polling and no interrupts to waste bus bandwidth. Constant rate is also possible if desired.
Fully Configurable to Generate Any Legal/Corner/Error Test Cases
Although the DUT interfaces are read and written by the interface adaptors, the contents that pass through the interface are fully controlled by software intelligently, including error injection and gaps between valid data. The software is running on a Linux PC that is connected to the other side of the PCI or PCIE core. A large portion of EDIM software is actually shared by both EDIM and the behavioral model. The EDIM software is layered and modular, starting from PCI driver to DIM manager, under the multi-thread computing environment that is provided by ADG. As other Draco components, EDIM is controlled in SDL at the usage level. In fact, the functional equivalence is achieved by conceptually taking out behavioral code and replaced it with the interface adaptor and its driver. EDIM can be manipulated with PRTG for creating new test case automatically.
Open Architecture for Adding New Interfaces
EDIM has shared bus architecture to reduce the IO pin count when mapped into an FPGA board. It uses open and free
bus to connect different interfaces. WISHBONE bus is chosen for its scalability and good performance.
EDIM for Ethernet X/G/MII Interface
An EDIM that supports X/G/MII interface is available. This Ethernet EDIM has 16 ports, although it is scalable and the fewer ports, the faster speed. Each port can be independently set to XGMII, GMII, or MII modes. XGMII is for 10G port, GMII is for 1G port, and MII is for 10/ 100M ports. The following are the key features,
- X/G/MII interfaces
- Scalable in terms of clock frequency and number of ports
- Fully functional as Ethernet MAC for ASIC verification
- Functional equivalent to behavioral model but emulatable
- Alternative solution for Ethernet tester and slow-down bridge
- Fully configurable as objects in SDL
- Seamless integrated with other Draco components, such as ASIM, ADG, and PRTG.
- Precise control of preamble, ipg, and carrier extension
- Precise control of error injection
- Fast Ethernet (802.3u)
- Gaga-bit (802.3z, 802.3ab)
- 10Gbps (802.3ae)
- Flow control (802.3x)
- Link Aggregation (802.3ad)
- Logic Link Control (802.2, LLC/SNAP)
- Jumbo packet to any size
- VLAN tagging (802.1q)
Reference EDIM for ASIC Internal Memories
This reference EDIM uses Xilinx’s dual-ported memory primitives. One port is connected to WISHBONE bus and the other port can be tailored to model internal ASIC memories. This gives you the full controllability and observability of the ASIC memories.
Using EDIM as Monitor and Checker at Major Interface
You can design an EDIM that is connected to some important interface inside the ASIC. During the emulation, data can be collected and checked automatically against the ASIC C-model or golden data. This eases the debugging effort and increases productivity.
Develop Your Own EDIM for Any Interface
Because the hardware part is modular per interface and the software is layered and modular per functionality, a new EDIM that supports different ASIC interface can be added with ease. With the EDIM technology, you have the power to build a simulation environment that is also emulatable on an FPGA board. EDIM can also be de-coupled from the rest of the Draco components. For example, Ethernet EDIM can be used to replace Ethernet tester and the slow-down bridge as a cost-effective solution that has more functionality and granularity of control.