Fastest and Accurate PCIE Models

PCIE-VR has both cycle-accurate model (CAM) and transaction-level model (TLM).

  • Three kinds of APIs, i.e., C, Verilog, and DSC script for ease of programming.

  • Cycle-accurate Model (CAM) with PIPE, PCS, and serial interfaces.

  • Fastest Transaction Level Model for architecture design, test case development, and software-hardware co-verification.

  • Supports for multiple PCIE device instances in one PCIE-VR instance.

  • Supports for any verification language and test bench.

  • Supports for third-party architecture design tools.

  • TLM can be integrated to an emulator via the standard SCE-MI interface.

  • Fully configurable at run time better than compilation options.

  • Supports for simulation speed-up, such as zero-time configuration, backdoor access, state bypass, etc.

  • A rich set of User-Defined Functions for customization, such as performance analysis.

Realistic traffic: Multiple PCIE devices are modeled in one instance

Copyright 2005 Tarek Verification Systems. All rights reserved.