PCIE-VR Lite

The Lite version of PCIE-VR is for FPGA designers who need to verify DMA and other sophisticated features. Because debugging FPGA in the lab is very time consuming, PCIE-VR Lite can be integrated with your design as a full functional root complex, bridge, or end point. You can be confident that your design will work before going to the lab.

Not only can you integrate PCIE-VR Lite onto an existing test bench in a few hours (plug&play), you can also choose your favorite language, either Verilog, System Verilog, or VHDL, C, to write tests. 

Features

  1. All PCIE standards, Gen1, Gen2, and Gen3

  2. Standard interfaces, serial, PIPE, 8/10b, and parallel

  3. Root complex is a complete CPU sub-system

    • Unlimited size for host memory definition

    • Multi-Threaded

  4. Running on Linux, Windows, and SunOS

  5. Programming API in Verilog, SystemVerilog, and C

  6. Automatic multi-threaded TLP generation without programming

    • Bar initialization thread

    • Performance measurement

    • Advanced TLP verification

For Xilinx Users

  1. Plug&Play Test Bench for Xilinx PCIE IP cores

    • Complete Verilog Test Bench and scripts. Integrated with your design in a few hours.

    • Best performance insimulation, 8x faster with UltraScale Kintex PCIE Gen3 core

  2. Verified with the following Xilinx PCIE IP cores:

    • UltraScale Kintex PCIE Gen3 Integrated Core, V3.1 (8 lanes)

      • ​Both PIPE and serial interfaces

    • Virtex-7 End Point V3.6 (8 lanes)

    • Virtex-7 End Point Block Plus V1.6 (8 lanes), V1.10 (4 lanes)

    • Virtex-7 End Point PIPE V1.7 (1 lane)