Physical Layer Verification Automation

  • Plug&Play verification.

  • Sophisticated LTSSM state exerciser automatically and exhaustively performs endless state transition looping.

  • Supports for parallel, 8/16-bit PIPE, 10/20-bit PCS, and serial interfaces.

  • Supports all Gen2 new features, such as speed change, up configure, modified polling compliance, etc.

  • Fully modeled the logical sub-block.

  • Supports x1, x2, x4, x8, x12, x16, and x32 lanes in run-time.

  • Automatic link training and initialization or bypass.

  • Supports for lane to lane skew/de-skew, lane reversal, and link error recovery, etc.

  • Supports multi-level error injections down to any bit with powerful automatic control without programming.

  • Supports for clock jitter effect and elastic buffer model.

  • Automatic and configurable L0s/L1 exit latency calculation.

  • LTSSM state exerciser example source code for DUT.

    Running From State to State Endlessly and Thoroughly

    LTSSM State Exerciser Exhaustively Loops Through All the States

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